
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:25:57 03/04/2012
-- Design Name:   RegFile
-- Module Name:   C:/Xilinx92i/PROJECTAIC/tb_RegFile.vhd
-- Project Name:  Procesador
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RegFile
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
use IEEE.std_logic_arith.all;

ENTITY tb_RegFile_vhd IS
END tb_RegFile_vhd;

ARCHITECTURE behavior OF tb_RegFile_vhd IS 
--	type RegisterBank is array (7 downto 0) of STD_LOGIC_VECTOR (7 downto 0);
--	signal regArray : RegisterBank := ("00000000", "00000001","00000010",
--											"00000011","00000100","00000101",
--											"00000110","00000111");

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT RegFile
	PORT(
		rs1 : IN std_logic_vector(2 downto 0);
		rs2 : IN std_logic_vector(2 downto 0);
		rd : IN std_logic_vector(2 downto 0);
		clk : IN std_logic;
		rf_sel : IN std_logic;
		w_sel : IN std_logic;
		dataRegister_o : IN std_logic_vector(7 downto 0);
		data_acc_o : IN std_logic_vector(7 downto 0);          
		r1 : OUT std_logic_vector(7 downto 0);
		r2 : OUT std_logic_vector(7 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL clk :  std_logic := '0';
	SIGNAL rf_sel :  std_logic := '0';
	SIGNAL w_sel :  std_logic := '0';
	SIGNAL rs1 :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL rs2 :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL rd :  std_logic_vector(2 downto 0) := (others=>'0');
	SIGNAL dataRegister_o :  std_logic_vector(7 downto 0) := (others=>'0');
	SIGNAL data_acc_o :  std_logic_vector(7 downto 0) := (others=>'0');

	--Outputs
	SIGNAL r1 :  std_logic_vector(7 downto 0);
	SIGNAL r2 :  std_logic_vector(7 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: RegFile PORT MAP(
		rs1 => rs1,
		rs2 => rs2,
		rd => rd,
		clk => clk,
		rf_sel => rf_sel,
		w_sel => w_sel,
		dataRegister_o => dataRegister_o,
		data_acc_o => data_acc_o,
		r1 => r1,
		r2 => r2
	);


	clk <= not clk after 25 ns; -- periodo de 50 ns

	tb : PROCESS
	BEGIN

		-- Wait 100 ns for global reset to finish
		wait for 49 ns;
		
		
	--primero escribimos en el banco de registros, 
	--asignando a cada registro el valor de su indice
	
	
		rf_sel <= '0';
		--empezamos con dataRegister_o
		w_sel <= '0';
		
		rd <= conv_std_logic_vector(1,3);
		dataRegister_o <= conv_std_logic_vector(1,8);
		wait for 50 ns;
		rd <= conv_std_logic_vector(2,3);
		dataRegister_o <= conv_std_logic_vector(2,8);
		wait for 50 ns;
		rd <= conv_std_logic_vector(3,3);
		dataRegister_o <= conv_std_logic_vector(3,8);
		wait for 50 ns;
		
		--ahora probamos con data_acc_o
		w_sel <= '1';
				
		rd <= conv_std_logic_vector(4,3);
		data_acc_o <= conv_std_logic_vector(4,8);
		wait for 50 ns;
		rd <= conv_std_logic_vector(5,3);
		data_acc_o <= conv_std_logic_vector(5,8);
		wait for 50 ns;
		rd <= conv_std_logic_vector(6,3);
		data_acc_o <= conv_std_logic_vector(6,8);
		wait for 50 ns;
		rd <= conv_std_logic_vector(7,3);
		data_acc_o <= conv_std_logic_vector(7,8);
		wait for 50 ns;
		
		--aqui cada registro ha de tener el valor de su indice,
		--lo que vamos a comprobar con la lectura
		
		
							
	--probamos lectura (r2 ha de ser igual a rs2 y r1 a rs1)
		rf_sel <= '1'; --habilitamos lectura
		rs1 <= conv_std_logic_vector(1,3);
		rs2 <= conv_std_logic_vector(2,3);		
		
		wait for 50 ns;
		
		assert (r1 = conv_std_logic_vector(1,3))
				report "Error en lectura/escritura de R1"
				severity FAILURE;
		assert (r2 = conv_std_logic_vector(2,3))
				report "Error en lectura/escritura de R2"
				severity FAILURE;		
				
		
		
		
		rs1 <= conv_std_logic_vector(3,3);
		rs2 <= conv_std_logic_vector(4,3);		
		wait for 50 ns;
		
		
		assert (r1 = conv_std_logic_vector(3,3))
				report "Error en lectura/escritura de R3"
				severity FAILURE;
		assert (r2 = conv_std_logic_vector(4,3))
				report "Error en lectura/escritura de R4"
				severity FAILURE;		
		
		rs1 <= conv_std_logic_vector(5,3);
		rs2 <= conv_std_logic_vector(6,3);				
		wait for 50 ns;
		
		
		assert (r1 = conv_std_logic_vector(5,3))
				report "Error en lectura/escritura de R5"
				severity FAILURE;
		assert (r2 = conv_std_logic_vector(6,3))
				report "Error en lectura/escritura de R6"
				severity FAILURE;		
		
		rs1 <= conv_std_logic_vector(7,3);
		rs2 <= conv_std_logic_vector(0,3);
										
		wait for 50 ns;
		
		
		assert (r1 = conv_std_logic_vector(7,3))
				report "Error en lectura/escritura de R7"
				severity FAILURE;
		assert (r2 = conv_std_logic_vector(0,3))
				report "Error en lectura/escritura de R0"
				severity FAILURE;		
										
										
		-- Place stimulus here


		 report ("**********TESTS DE RegFile SUPERADOS**********")
		 severity NOTE;

		wait; -- will wait forever
	END PROCESS;

END;
